1. Field of the Invention
The present invention relates to a digital data comparing circuit for a digital signal, more particularly to a digital data comparing circuit used for a microprocessor and a digital signal processor (hereinafter referred to as a DSP).
2. Description of the Related Art
When magnitudes of two data are compared, absolutes values of the two data are sometimes compared in case where the two data have different algebraic signs. For example, such comparison processing is needed at the time of peak detection of voice data.
In general, as a representation style of sign-bearing data, a notation has been adopted using a two's complement. In order to obtain an absolute value of data represented by the style of the two's complement, the total data must be first logically inverted in response to a sign bit of the data. Thereafter, a number "1" must be added to the least significant bit (LSB). Specifically, if the data is a negative number, its two's complement becomes an absolute value, and the two's complement can be obtained by adding the number "1" to one's complement. Therefore, the total of the data is logically inverted and the number "1" is added to the least significant bit of this logically inverted data. If the data is a positive number, a value of the data becomes an absolute value. As a result, in order to make a comparison for the absolute values, an adder must be prepared in addition to an operation circuit for making the comparison.
Therefore, in order to make a comparison for the absolute values of the numbers represented according a notation of the two's complement style, a method in which absolute values of all of the data are previously computed and the values of the absolute values are subsequently compared is employed. Or, a method in which comparison for the absolute values of all of the data are made while computing the absolute values of all of the data is also employed.
FIG. 1 shows a conventional example of an absolute value comparing circuit for simultaneously executing both of computation of an absolute value and a comparison operation. Hereinafter, the same symbols are given to the same components and descriptions for them are omitted. Referring FIG. 1, reference symbols X and Y denote data of multi bits represented according to the notation of the two's complement style. Moreover, sign bits of the data X and Y, that is, the most significant bits (MSB), shall be represented by "a" and "b", respectively.
A circuit for obtaining an absolute value U of the data X consists of an selective inverter 2a and an incrementer 3a. The data X is supplied to a data input terminal of the selective data inverter 2a, and the signal a is supplied to a control terminal thereof. The data selective inverter 2a inverts the data X to output as data X', if the data is a negative number, that is, if the signal "a" is high in a logic level. When the data X is a positive number, that is, if the signal "a" is low in the logic level, the inverter 2a outputs the as-received data X as the data X' without inverting it.
The incrementer 3a comprises a data input terminal and a control terminal, and the data input terminal thereof is supplied with the data X' and the control terminal thereof is supplied with the signal "a". If the data X is a negative number, that is, the signal "a" is high in the logic level, the incrementer 3a adds a number "1" to the least significant bit of the data, and outputs it as data U. When the data is a positive number, that is, the signal "a" is low in the logical level, the incremeter 3a outputs the as-received data X' as the data U without adding the number "1" to the least significant bit of the data X'.
Similarly, a circuit for obtaining an absolute value V of data Y consists of a selective data inverter 2b and an incrementer 3b. Both of the data U and V are supplied to input terminals of a magnitude comparator 1, respectively. The magnitude comparator 1 compares the data U and V, and outputs the comparison result as a flag SF. The flag SF takes the value represented by means of SF=0 when U.gtoreq.V is satisfied, and takes the value represented by means of SF=1 when U&lt;V is satisfied.
FIG. 2 shows a circuit example of the selective data inverter 2a. This circuit is for a data width of four bits. X3 to x0 show from the most significant bit to the least significant bit of the data X in this order. x'3 to x'0 show from the most significant bit to the least significant bit of the data X' in this order.
As is shown in FIG. 2, each of first input terminals of exclusive OR gates 4a to 4d is supplied with a most significant bit data a, and each of second input terminals or the exclusive OR gates 4a to 4d is supplied with x3 to x0. Output terminals of the exclusive OR gates 4a to 4d output x3' to x0' as output signals, respectively.
The selective data inverter 2b has the same constitution as that of the selective data inverter 2a shown in FIG. 2.
FIG. 3 shows an example of a circuit constitution of the incrementer 3a shown in FIG. 1. The circuit of the incrementer 3a is for a data width of four bits. Referring to FIG. 3, reference symbols 5a to 5d denote exclusive OR gates, respectively, and reference symbols 6a to 6c denote AND gates, respectively. Furthermore, reference symbols u3 to u0 denote from the most significant bit to the least significant bit of the data U in this order.
As is shown in FIG. 3, the signal a is supplied to first input terminals of the exclusive OR gate 5a and the AND gate 6c, and the signal x0' is supplied to second input terminals thereof. An output terminal or the AND gate 6c is connected to respective first input terminals of the exclusive OR gate 5c and the AND gate 6b, and the signal x1' is supplied to respective second input terminals thereof. An output terminal of the AND gate 6b is connected to respective first input terminals of the exclusive OR gate 5b and the AND gate 6a, and the signal x2' is supplied to respective second input terminals thereof. A first input terminal of the exclusive OR gate 5a is connected to an output terminal of the AND gate 6a, and a second input terminal of the exclusive OR gate 5a is supplied with the signal x3'. Moreover, output signals from the exclusive OR gates 5a to 5d are u3 to u0, respectively.
The incrementer 3b also has the same circuit constitution as that of the incrementer 3a shown in FIG. 3.
FIG. 4 shows an example of a circuit constitution of the magnitude comparator 1 shown in FIG. 1. This circuit of the magnitude comparator 1 is for a data width of four bits.
Referring to FIG. 4, reference symbols 7a to 7d denotes inverters; 8a to 8c, exclusive NOR gates; 9a to 9d, AND gates; and 10, an OR gate. Moreover, reference symbols V3 to V0 denote from the most significant bits to the least significant bits in this order.
An operation of the absolute value comparing circuit shown in FIG. 1 will be described below. First, the data X and Y to be compared, which are represented according to the notation in the two's complement style, are input to the conventional absolute value comparing circuit.
Next, when the data X and Y indicate negative numbers, that is, when the sign bits a and b or the data X and Y are high in a logic level, the selective data inverters 2a and 2b inverts all bits of the data X and Y and output the inverted data. When the data X and Y indicate positive numbers, that is, when the sign bits a and b of the data X and Y are low in the logic level, the selective data inverters 2a and 2b output the as-received input data X and Y without inverting them.
Thereafter, when the sign signals a and b are high in a logic level, the signals a and b are added to the least significant bit of the data output from the selective data inverter 2 by means of the incrementers 3a and 3b, respectively. On the other hand, the sign signals a and b are low in level, the as-received data X' and Y' are output as the data U and V. As described above, the absolute values U and V of the binary numbers X and Y represented according to the notation of the two's complement style are computed.
The absolute values .vertline.x.vertline. and .vertline.Y.vertline. computed in the above described manner are subjected to a judgment for their magnitude relation between them by means of a non-sign magnitude comparator 1. As a result of the judgment,
when .vertline.X.vertline.&lt;.vertline.Y.vertline. is satisfied, the flag SF equal to one is output from the magnitude comparator 1, when .vertline.X.vertline..gtoreq..vertline.Y.vertline. is satisfied, the flag SF equal to zero 0 is output therefrom.
However, the foregoing conventional absolute value comparing circuit has a disadvantage in that it has a comparatively large circuit scale. For this reason, the conventional absolute value comparing circuit has never been built in a microprocessor. In order to compare the absolute values of the data X and Y using the microprocessor in which the absolute value comparing circuit is not built-in, there are the following two ways.
The first way is the one in which the absolute values of the data X and Y are compared after computations for the absolute values of them. Since this way requires memory areas for storing the absolute values of the data X and Y, a large number of memory areas are occupied when a large number of the data X and Y exist like time variant sequential data. Moreover, the first way has a disadvantage in that the comparisons for the absolute values of data X and Y can not be performed until the computations for all of the absolute values of the data X and Y are completed.
The second way is the one in which comparisons for the absolute values of the data X and Y are performed every time of computation for the absolute values of them. In this way, though the memory areas are never occupied because of computations of the absolute values of the data X and Y, an operation time equivalent to one machine cycle is needed for the computation for the absolute value .vertline.X.vertline. of the data X, an operation time equivalent to one machine cycle is needed for the computation for the absolute value .vertline.Y.vertline. of the data Y, and an operation time equivalent to one machine cycle is needed for the comparison for both of the absolute values .vertline.X.vertline. and .vertline.Y.vertline.. Therefore, the comparison results can be obtained every three machine cycles. This implies that an operation time three times as long as that of the case where the foregoing absolute comparing circuit is built in the microprocessor is needed. A longer time than that operation time is actually consumed because of transferring of the data and the like.